Calculation of a scalar product in a direct-type FIR filter

ABSTRACT

The invention relates to a direct-type FIR filter, a method for calculating a scalar product in a FIR filter, and a method for designing a direct-type FIR filter. Successive words of a digital input signal are delayed in a delay line having delays (50A-50D) of the duration of one word, and the scalar product between the variously delayed words derived from the delay line and the corresponding constant coefficients is calculated. In accordance with the invention, calculation of the scalar product comprises a) combining the bits of words at the input (X0) and outputs (X1-X4) of the delay line bit by bit in a network of bit-serial subtractor and/or adder elements (51-56) wherein at least one of the bit-serial elements is involved in the multiplication operation of at least two different coefficients, and b) multiplying (49A-K) the multiplication results from the network by powers of two, and summing together (45-48) the results to yield the scalar product.

FIELD OF THE INVENTION

The present invention relates to a digital direct-type FIR filter, andin particular to calculation of a scalar product in a direct-type FIRfilter.

BACKGROUND OF THE INVENTION

A digital filter is a software or a specially designed electroniccircuit processing discrete digital signal samples to perform a desiredtransfer function operation on said signal. The Z transfer function of adigital, i.e. discrete time, FIR (Finite Impulse Response) filter hasthe generic form ##EQU1## where H(z) is the transfer function of thefilter, Y(z) and X(z) represent the output and input of the filterrespectively, a_(i) represent constant coefficients, i.e. tapcoefficients, and z^(-i) represents a delay of i samples. The propertiesof a FIR filter are solely dependent on the tap coefficients a_(i), andthus determination of these coefficients is required in order to obtainthe desired characteristics for the filter. There are several methodsfor determining the coefficients. The non-recursive discrete time filterin accordance with equation (1) is normally represented as a blockdiagram as shown in FIGS. 1 and 2. FIG. 1 illustrates a direct-type FIR(Finite Impulse Response) filter and FIG. 2 a transposed FIR filter. Thefiltering function in accordance with equation (1) can be realized byboth types of discrete time filter, but the present invention relates toa direct-type FIR filter according to FIG. 1. As is apparent from FIGS.1 and 2, the discrete time filter is illustrated as a block diagramwherein square blocks 1 perform delaying of the information by onesample z⁻¹, triangular blocks 2 represent multiplication operations, andcircles 3 represent adders.

As stated previously, the characteristics of the filter are dependent onthe values of the tap coefficients a_(i). Prior art direct-type FIRfilters exist in which a discrete multiplier unit for each tapcoefficient is employed. The drawback of this approach is the largenumber of multiplier units required, which occupy a considerable area ona semiconductor chip when embodied as an integrated circuit and aretherefore costly. A prior art approach is known in which the tapcoefficients are simple sums of powers of two, i.e. the coefficients arelimited to the form 2^(-a) +2^(-b) +2^(-c). Such an approach is attendedby the drawback of limitations in the possible coefficients to berealized. These limitations can substantially complicate the realizationof the desired signal processing function H(z).

Still another prior art solution entails the use of a fast multiplierand memory for realizing the filter. Such a solution is illustrated inFIG. 3, wherein the necessary delays z⁻¹ are generated by buffering thevalues of the input signal X(z) into a RAM memory 41 prior to inputtingthem to a multiplier 42, in which they are multiplied by coefficientsa_(i) derived from a ROM memory. Thereafter the multiplication resultsare supplied to an adder 44 wherein they are summed with the filteroutput Y(z). The drawback of such a solution is the chip area occupiedby the fast multiplier unit 42. Further drawbacks include the high powerconsumption of the multiplier unit 42 and, in certain applications, theelectromagnetic interference produced thereby in other circuitry.Furthermore, on account of the limited speed of the multiplier unit,only a limited number of coefficients a_(i) can be realized with onemultiplier unit. Complex structures require several multiplier units anda complex control logic.

DISCLOSURE OF THE INVENTION

The object of the present invention is a direct-type digital FIR filterthat can be embodied as an integrated circuit with several coefficientsso as to occupy substantially less chip area in integrated circuitconfiguration than the filters implemented by the prior art techniques.

Another object of the present invention is a digital filter suitable forcomparatively high clock frequencies.

A further object of the present invention is a digital filter enablingrealization of arbitrary coefficients automatically.

These and other objects and advantages of the invention are achievedwith a method for calculating a scalar product in a direct-type digitalFIR filter, the method comprising

delaying successive words of a digital input signal in a delay linehaving delays of the duration of one word, and calculating the scalarproduct between the variously delayed words derived from the delay lineand the corresponding coefficients,

the method being characterized in that the calculation step comprises

combining the bits of words at the input and outputs of the delay linebit by bit in a network of bit-serial subtractor and/or adder elementswherein at least one of said bit-serial subtractor and/or adder elementsis involved in the multiplication operation of at least two differentcoefficients,

multiplying the multiplication results from the network of bit-serialsubtractor and/or adder elements by powers of two, and summing togetherthe results to yield said scalar product.

Another aspect of the invention is a direct-type digital FIR filter,comprising

a delay line having an input for receiving digital words in serial form,a plurality of one-word delays and an output after each delay;

calculation means for calculating the scalar product between the wordsat the input and each output of the delay line and the correspondingcoefficients;

an output to which the calculated scalar product is applied,

the filter being characterized in that said calculation means comprise

a plurality of bit-serial subtractor and/or adder elements for combiningbits of words at the input and each output of the delay line, saidbit-serial subtractor and/or adder elements forming a network wherein atleast one of said bit-serial subtractor and/or adder elements isinvolved in the multiplication operation of at least two differentcoefficients,

means for multiplying the multiplication results from the network ofbit-serial subtractor and/or adder elements by powers of two and summingtogether the results to yield said scalar product.

One aspect of the invention is a method for designing a direct-typedigital filter, comprising a step of determining the coefficientsrequired in the filter. This method is characterized in accordance withthe invention by further steps of

designing a network of bit-serial subtractor and/or adder elements forthe filter, wherein the number of said bit-serial elements is minimizedtaking into account performance criteria of the filter, so that amaximum number of said bit-serial elements are involved in themultiplication operation of more than one different coefficients,

designing an output register performing multiplication by a power of twoand summing together the results from said network, said registercomprising one-bit delay elements and bit-serial adder and subtractorelements.

In the present invention, the scalar product is calculated by combiningvalues derived from the delay line in bit-serial adder and/or subtractorelements, so that at least some of the adder and/or subtractor elementsare used to provide the mantissa of more than one coefficient. In otherwords, the "partial sum" or "partial difference" outputted by a specificadder or subtractor element can be used on the next level of the adderand/or subtractor element network to produce the mantissas of severalcoefficients simultaneously. Furthermore, in the arrangement of theinvention the combined use of adder and subtractor elements in producingthe coefficients enables the number of calculation elements(+/-operators) to be minimized. The products given by the network ofcalculation elements are multiplied by the exponent of the respectivecoefficient and summed together to produce the final scalar product. Thearrangement of the invention affords good round-off and truncationbehaviour. The scalar product is rounded off or truncated only once, andthus the error in the scalar product is, on an average, only 1/2 leastsignificant bits. Multiplication by a power of two and summation arepreferably performed on all coefficients in the same output register,which is comprised of one-bit delays and bit-serial adder and subtractorelements. Thus the number of necessary delays can be optimized ascompared with a case where each coefficient has dedicated calculationelements, delay elements, for multiplication by a power of two.

By means of the invention, the network of bit-serial adder andsubtractor elements can be optimized by finding the sum and/ordifference of powers of two for the coefficients required, so as toconsiderably diminish the requisite number of calculation elements incomparison with the prior art solutions. At the same time, the requisitenumber of series-connected elements is characteristically diminished.With the construction of the invention, arbitrary coefficients can berealized. Still another advantage of the invention is a low number oflogic levels, and thus the maximum operating frequency is very high.When the invention is realized as an integrated circuit, the siliconarea occupation required is less than half the area required by thedigital filter shown in FIG. 3 which includes a multiplier and RAM andROM memories.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following the invention will be set forth by means of preferredembodiments with reference to the accompanying drawing, wherein

FIG. 1 is a block diagram of a direct-type digital FIR filter,

FIG. 2 is a block diagram of a transposed digital FIR filter,

FIG. 3 is a block diagram of a prior art digital filter implemented by afast multiplier and memories,

FIG. 4 is a block diagram of a digital filter of the invention with fivecoefficients,

FIG. 5 is a block diagram of an embodiment of the digital filter of FIG.4, and

FIG. 6 is a block diagram of a bit-serial adder element.

PREFERRED EMBODIMENT OF THE INVENTION

Reference will now be made to FIG. 4, showing a five-coefficientdirect-type digital FIR filter implemented in accordance with theinvention. After the input IN, the filter comprises a delay line havingfour delay blocks 50A, 50B, 50C and 50D, each having a length of oneword (z⁻¹). Each delay block is made up of N one-bit delay elements 49,as in delay block 50D in FIG. 5. N is the word width of the filter. Thenumber sequence X obtained at the input IN is supplied to delay line50A-50D in bit-serial form, each value as N successive bits, the leastsignificant bit LSB occurring first. The words are clocked through thedelay line in such as way that each word is shifted one bit at eachclock cycle. In other words, during N successive clock cycles each bitof word appears in turn at the one-bit output of the respective delayblock. Thus the delay line 50A-50D (the input included) provides anoutput of five variously delayed values x₀, x₁, x₂, x₃ and x₄ inbit-serial form. The values thus obtained should be multiplied by thecorresponding tap coefficients a₀, a₁, a₂, a₃ and a₄, whereafter theproducts obtained are summed together to give the desired scalarproduct, as in the schematic block diagram of a direct-type FIR filterof FIG. 1.

A network of combining elements 51, 52, 53, 54, 55 and 56 is coupled tothe outputs of the delay line for multiplication of the words x0-x4 bytap coefficients a₁ -a₄ by combining the one-bit outputs of the delayline. The network of combining elements comprises bit-serial adder andsubtractor elements 51, 52, 53, 54, 55 and 56 employing bit-serialarithmetic on several levels. In accordance with the basic concept ofthe invention, it has been sought to minimize the number of calculationelements taking into account certain performance criteria for thefilter, so that the same calculation elements are employed to producemore than one different tap coefficients. In the exemplary case of FIG.4, five coefficients are formed by employing only six bit-serial(one-bit) arithmetic elements. For instance, the inputs of the adderelement 53 are provided by the outputs x₂ and x₃ of the delay line. Onthe other hand, the output value x₂ +x₃ of the adder element 53 providesan input for adder elements 52 and 54 on the next network level. Thecalculation elements 51, 52, 54, 55 and 56 respectively provide fiveoutputs, which are then multiplied by the requisite power of two inmultiplier units 57A, 57B, 57C, 57D and 57E. The outputs of multiplierunits 57A-57E are summed together in an adder 58 to obtain the desiredscalar product ##EQU2##

Delaying of a bit-serial value for the duration of one bit correspondsto multiplying the value by two. Therefore, the multiplier units 57A-57Ehave in one embodiment of the invention been configured by using one-bitdelay elements, one delay element for each power of two. Thus forexample multiplier unit 57A has nine one-bit delays and multiplier unit57D three one-bit delays. Hence the embodiment of FIG. 4 requires atotal of 23 one-bit delay elements to implement the multiplier units57A-57D.

FIG. 5 shows the preferred embodiment of the invention, in whichelements and functions similar to those in FIG. 4 are denoted by thesame reference numerals and symbols. In the embodiment of FIG. 5, thedelay line 50A-50D and the network of calculation elements 51-56 areidentical with those of the embodiment of FIG. 4. On the other hand, themultiplier units 57A-57D and adder 58 of FIG. 4 are replaced by a commonoutput register in FIG. 5. The output register comprises a seriesconnection of the following elements in the given order: three one-bitdelay elements 49A, 49B and 49C, an adder 45, a one-bit delay element49D, an adder 46, two one-bit delay elements 49E and 49F, a subtractor47, three one-bit delay elements 49G, 49H and 49K, and an adder 48. Inthe network of calculation elements 51-56, the output of element 51 iscoupled to the input of delay element 49A, the output of element 52 iscoupled to adder 45 together with the output of delay element 49C, theoutput of element 54 is coupled to adder 46 together with the output ofdelay element 49D, the output of element 55 is coupled to subtractor 47together with the output of delay element 49F, and the output of element56 is coupled to adder 48 together with the output of delay element 49K.The output of adder 48 provides the output OUT for the filter. Thecalculation elements 45, 46, 47 and 48 are bit-serial calculationelements. The embodiment of FIG. 5 employs common delays for differentcoefficients, thus enabling further reduction in the number of elementsrequired for the filter. In the exemplary case, the output registercomprises nine delay elements and four calculation elements, while thecorresponding operation in the embodiment of FIG. 4 requires 23 delayelements and one calculation element.

The operation of the filter of the invention will be describedhereinbelow with reference to the embodiment of FIG. 5. All calculationelements 51-56, 45-48 and delay elements 49A-49K of the output registerare reset to zero at the start of the calculation. The advantages of thefilter in accordance with the invention include the fact that all theseelements can be reset simultaneously, and the resetting can be performedwith a single control signal. Thereafter a new value x0 is clocked tothe delay line 50A-50D, and thus the values x₁ -x₄ clocked to the delayline during the previous calculation cycles are shifted one delay blockforward. During the next N clock cycles, the values x₀, x₁, x₂, x₃ andx₄ with mutually different delays are thus derived bit by bit inbit-serial form as outputs from the delay line. The bit-serial values x₀-x₄ derived from the delay lines are applied to the bit-serialcalculation network 51-56, the outputs of which yield bit-serial valuesx₀ -x₂, x₁ +x₂ +x₃, x₀ +x₂ +x₃ +x₄, x₀ +x₄ and x₃ -x₄. The values thusobtained from the calculation network 51-56 are applied in bit-serialform to the output register that combines them, simultaneously delayingthem for various periods of time. As stated previously, delaying abit-serial value for one bit corresponds to multiplying the value bytwo. Hence in the embodiment of FIG. 5 the output register delays theinput values by 9, 6, 5, 3 and 0 bits, which corresponds to multiplyingthe values by 512, 64, 32, 8 and 1 respectively. Thus the value of theoutput OUT of the output register gives the value

    512(x.sub.0 -x.sub.2)+64(x.sub.1 +x.sub.2 +x.sub.3)+32(x.sub.0 +x.sub.2 +x.sub.3 +x.sub.4)-8(x.sub.0 +x.sub.4)+(x.sub.3 -x.sub.4)=536x.sub.0 +64x.sub.1 -416x.sub.2 +97x.sub.3 +23x.sub.4 =r           (3)

After the entire word to be loaded in has been clocked bit by bit to thedelay line 50A-50D and the calculation network 51-56 during N clockcycles, there are still numbers significant for the calculation in theoutput register and in the values stored in the calculation network51-56. In order that the final product may be outputted from the filter,clocking of the delay line 50A-50D and the calculation network 51-56 iscontinued for further ten clock cycles, whereupon the entire product isderived. When calculation is performed in accordance with the foregoing,the word width of the product in the filter increases considerably. Ifit is not desired to take advantage of this, n first bits of the productclocked from the adder 48 to the output OUT are omitted. Thiscorresponds to dividing the product by 2^(n). If for example in theembodiment of FIG. 5 ten first output bits are omitted at the outputOUT, the filter has the calculated function ##EQU3##

FIG. 6 shows a block diagram of a bit-serial adder element. The adderelement comprises a one-bit delay block 61, which in this exemplary caseis implemented by a D flip-flop, and an adder 62 adding up two data bitsand outputting a sum and a carry bit c_(out). All signals shown in FIG.6 are one-bit signals, i.e. each of them can be implemented by a singlesignal line. The adder element shown in FIG. 6 operates in the followingway. The values to be summed together are applied to the adder 62 inserial form, the least significant bit (LSB) being the first. The addingup of two bits a and b and a carry bit c_(in) gives as a result one sumbit sum and a carry bit c_(out) which is stored in the delay block 61for summing together the next bits. The delay block 61 is reset betweenthe addition of two successive N-bit values by way of the reset line.

The bit-serial subtractor element can be embodied similarly. The onlydifference is that instead of an adder 62, a subtractor is employed.Furthermore, the delay block 61 is set to the value 1 between thesubtraction of two successive N-bit values.

The figures and the description relating to them are only intended toillustrate the present invention. In their details, the methods andfilter of the invention can vary within the purview of the accompanyingclaims.

What is claimed is:
 1. A method for calculating a scalar product betweena succession of serially ordered words of a sampled and digitized inputsignal in a direct-type digital FIR filter, the method comprising thesteps of:providing the succession of serially ordered words of thesampled and digitized input signal; delaying each of the succession ofserially ordered words of the sampled and digitized input signal by atleast one period of a duration of the sampling of one serially orderedword of the sampled and digitized input signal; selectively adding andsubtracting in a bit serial fashion selected serially ordered words ofthe sampled and digitized input signal to produce a group coefficientmultiplications of at least two of the serially ordered words; bitserially multiplying the coefficient multiplications by multiple powersof two to form a plurality of partial scalar products; and bit seriallysumming together all the plurality of partial scalar products to yieldsaid scalar product.
 2. The method for calculating a scalar product ofclaim 1 wherein bit serial multiplying is accomplished by delaying eachof the partial scalar products by a selected delay period to shift saidscalar product to perform a multiplication by a power of two.
 3. Themethod for calculating a scalar product of claim 1 wherein the bitserial summing is accomplished by selectively adding and subtracting thepartial scalar products to accumulate the plurality of partial scalarproducts.
 4. A method of direct-filtering of a signal comprising thesteps of:sampling and digitizing said signal to form a succession ofdigital words representing the amplitude of said signal; bit wiseserially ordering each digital word of said succession of digital words;delaying each of the succession of serially ordered words of the sampledand digitized input signal by at lease one period of a duration of thesampling of one serially ordered word of the sampled and digitized inputsignal; selectively adding and subtracting in a bit serial fashionselected serially ordered words of the sampled and digitized inputsignal to produce a group coefficient multiplications of at least two ofthe serially ordered words; bit serially multiplying the coefficientmultiplications by multiple powers of two to form a plurality of partialscalar products; and bit serially summing together all the plurality ofpartial scalar products to yield one scalar product; and converting asuccession of said scalar products to a direct-filtered signal.
 5. Themethod of direct-filtering of a signal of claim 4 wherein bit serialmultiplying is accomplished by delaying each of the partial scalarproducts by an selected delay period to shift said scalar product toperform a multiplication by a power of two.
 6. The method ofdirect-filtering of a signal of claim 4 wherein the bit serial summingis accomplished by selectively adding and subtracting the partial scalarproducts to accumulate the plurality of partial scalar products.
 7. Ascalar product calculator to calculate a scalar product betweensuccession of serially ordered words of a sampled and digitized inputsignal in a direct-type digital FIR filter, comprising:a plurality ofword delay elements to receive the succession of serially ordered wordsand delay each of the succession of serially ordered words by at leaseone period of a duration of the sampling of one serially ordered word ofthe sampled and digitized input signal; a plurality of adder/subtractorelements connected to the plurality of word elements and interconnectedwith other adder/subtractor elements to selectively add and subtract ina bit serial fashion selected serially ordered words of the sampled anddigitized input signal to produce a group coefficient multiplications ofat least two of the serially ordered words; a plurality ofmultiplication elements connected to the plurality of adder/subtractorelements to bit serially multiply the coefficient multiplications bymultiple powers of two to form a plurality of partial scalar products;and a summing element interconnected with the plurality ofmultiplication elements to bit serially sum together all the pluralityof partial scalar products to yield one scalar product.
 8. The scalarproduct calculator of claim 7 wherein each of the multiplicationelements is comprising a plurality of delaying elements to delay each ofthe partial scalar products by a selected delay period to shift saidscalar product to perform a multiplication by a power of two.
 9. Thescalar product calculator of claim 7 wherein the summing element iscomprising a plurality of adder/subtractor elements placed at the outputof multiplication elements to accumulate the plurality of partial scalarproducts.
 10. A digital direct-type digital filter to filter asuccession of serially ordered words of a sampled and digitized inputsignal, comprising:a plurality of word delay elements to receive thesuccession of serially ordered words and delay each of the succession ofserially ordered words by at lease one period of a duration of thesampling of one serially ordered word of the sampled and digitized inputsignal; a plurality of adder/subtractor elements connected to theplurality of word elements and interconnected with otheradder/subtractor elements to selectively add and subtract in a bitserial fashion selected serially ordered words of the sampled anddigitized input signal to produce a group coefficient multiplications ofat least two of the serially ordered words; a plurality ofmultiplication elements connected to the plurality of adder/subtractorelements to bit serially multiply the coefficient multiplications bymultiple powers of two to form a plurality of partial scalar products; asumming element interconnected with the plurality of multiplicationelements to bit serially sum together all the plurality of partialscalar products to yield one scalar product; and a plurality ofconverting elements connected to the output of the summing element toconvert a succession of said scalar products to a direct-filteredsignal.
 11. The digital direct-type digital filter of claim 10 whereineach of the multiplication elements is comprising a plurality ofdelaying elements to delay each of the partial scalar products by aselected delay period to shift said scalar product to perform amultiplication by a power of two.
 12. The digital direct-type digitalfilter of claim 10 wherein the summing element is comprising a pluralityof adder/subtractor elements placed at the output of multiplicationelements to accumulate the plurality of partial scalar products.
 13. Amethod for designing a direct-type digital FIR filter to filter asuccession of serially ordered words of a sampled and digitized inputsignal, comprising the steps of:creating a plurality of word delayelements to receive the succession of serially ordered words;determining a delay period of each of the succession of serially orderedwords, whereby each delay period is at least one period of a duration ofthe sampling of one serially ordered word of the sampled and digitizedinput signal; configuring interconnections of a plurality ofadder/subtractor elements to selectively add and subtract in a bitserial fashion selected serially ordered words of the sampled anddigitized input signal to produce a group coefficient multiplications ofat least two of the serially ordered words; configuring connections of aplurality of multiplication elements to bit serially multiply thecoefficient multiplications by multiple powers of two to form aplurality of partial scalar products; determining connections of asumming element to bit serially sum together all the plurality ofpartial scalar products to yield one scalar product; and providing aplurality of converting elements to convert a succession of said scalarproducts to a direct-filtered signal.
 14. The method of claim 13 whereinconfiguring each of the multiplication elements is configuring aplurality of delaying elements to delay each of the partial scalarproducts by an selected delay period to shift said scalar product toperform a multiplication by a power of two.
 15. The method of claim 13wherein providing the summing element is accomplished by creating anetwork of a plurality of adder/subtractor elements placed at the outputof multiplication elements to accumulate the plurality of partial scalarproducts.